1. Technical Field
This invention generally relates to integrated circuits, and more specifically relates to the area of microprocessor cores which are embedded on application-specific integrated circuits (ASICs).
2. Background Art
The proliferation of modern electronics is due in large part to the development of the integrated circuit. An application specific integrated circuit (ASIC) is a collection of logic and memory circuits designed to perform a specific task to meet the needs of a customer application. ASIC designs are implemented on a silicon die by mapping logic functions to a set of pre-designed, pre-verified logic circuits. These circuits range from the simplest functions to highly complex circuits referred to as "cores." Cores are typically high level industry-standard functions, such as a digital signal processor (DSP), an advanced RISC machines (ARM) microprocessor, an Ethernet function, or a peripheral component interconnect (PCI) controller. With a particular design in mind, customers can quickly assemble an ASIC design by using cores as building blocks. Such designs are commonly referred to as system level integration (SLI) or system on a chip (SOC).
In some ASIC designs, application code is embedded in read only memory (ROM) on the silicon die along with the circuitry that supports the execution of the application code. Typically, application code embedded in a system on a chip is the only application code that will ever use the circuitry on the ASIC, and since it is embedded, the code will never change. This type of ASIC design differs from a more traditional ASIC design where application code employing the chip is not embedded. When not embedded in the chip, the application code can be changed independently from the ASIC circuitry.
Traditional ASICs are designed to operate as generally as designers conceive necessary for the range of applications they will support. As a result, they include circuitry designed to support a wide range of applications. Thus, some circuitry designed into the ASIC might not be employed by any of the applications that employ the chip. Yet that unused circuitry is necessary from the design standpoint, to support unforseen application code changes. Therefore, in order to maximize the usefulness of an ASIC that will run non-embedded application code, unused circuitry is not removed and serves to assure that the ASIC will still operate in the case of changed, or new application code. For example, in the case of cores, all the general purpose core circuitry may not be employed by the independent applications using the ASIC. However, to maintain the usefulness of the industry standard grouping of circuitry making up the core, unused core circuitry is not removed from the design.
On the other hand, there is no reason to maintain unused circuitry in general purpose cores for ASIC designs in which all the application code that will ever use the circuitry is embedded on the chip. For such designs, a different approach can be used to maximize the amount of circuitry that can be placed on one silicon die. If circuitry in a general purpose core is not being used by any of the applications to be embedded on the chip, then the unused circuitry can be removed. The result is a "tailored" core, which has only the circuitry required to support the application code embedded on the ASIC. Advantages to tailoring cores, that is, advantages to removing unused circuitry, include lower power consumption and faster execution of the embedded applications, as well as smaller silicon area requirements. Thus, for systems on a chip, there is a need to tailor core circuitry, that is, to identify during ASIC design what circuitry will not be utilized by embedded applications and to remove it.
An example of unused core circuitry occurs in designing systems on a chip for use in cellular phones. Cellular phone applications require the use of digital signal processor (DSP) cores to enhance and filter sounds. While the global systems for mobile telecommunications (GSM) application heavily uses certain circuitry in the DSP core, other parts of that core are not required at all. Tailoring the core circuitry for this application would remove the unused parts of the DSP. For battery operated cellular phones, the advantages of lower power consumption and reduced silicon area that result from removing the unused core circuitry are critical. Thus, there is a need to tailor the general purpose DSP core in a system in a chip to be used in cellular phones.
A problem associated with the concept of tailoring cores is the labor required. To provide the advantages of reduced core circuitry in every system in a chip design, each general purpose core on the design would have to be tailored to the each of the applications embedded on the ASIC. Given that each ASIC design typically utilizes more than one core, and given the proliferation of ASIC use in the electronics industry today, the labor required to tailor ASIC cores can be significant. Thus, to tailor highly complex core circuitry to each ASIC design, an automated method of circuit reduction is certainly advantageous over non-automated methods.
A second problem associated with tailoring general purpose core circuitry is the need to preserve as much integrity of the original core design as possible. Since cores are pre-designed, pre-verified functional groupings of circuitry, all of the circuitry is there for a purpose. The process of tailoring cores needs to identify and remove circuitry whose purpose does not serve a specific set of applications. Sometimes circuitry in a general core design is unused during normal operation, but serves a purpose in the manufacture testing process, or to perform error recovery operations. Removal of that type of unused circuitry may corrupt the integrity of the original design. Thus, there is a need in tailoring cores to identify core circuitry which may not serve a specific set of application code directly, but which cannot be removed without corrupting the integrity of the core design.
In some ways, the concept of tailoring cores resembles other logic reduction tools that are used in circuitry design today. However, those tools do not address the specific needs associated with tailoring cores for use on systems in a chip. For example U.S. Pat. No. 4,960,724 "Method For Deleting Unused Gates And Method For Manufacturing Master-Slice Semiconductor Integrated Circuit Device Using The Deleting Method" (issued Oct. 2, 1990 to Watanabe et al. and assigned to Hitachi, Ltd.) discloses a method of tracing signal paths through a total circuit diagram, and deleting unconnected gates. However, Watanabe el al.'s method does not have any way of recognizing what circuitry should not be removed, even if unused. Nor is Watanabe et al.'s method automated.
Another group of patents address logic reduction by examining circuit utilization and deleting unused circuitry. U.S. Pat. No. 5,347,465 "Method Of Integrated Circuit Chips Design" (issued Sep. 13, 1994 to Ferreri et al. and assigned to IBM Corp.) and U.S. Pat. No. 4,602,339 "Method Of Manufacturing Master-Slice Integrated Circuit Device" (issued Jul. 22, 1986 to Aihara et. al. and assigned to Fujitsu Ltd.) both disclose methods to delete unconnected circuitry. However, neither of these methods take into account what application code will utilize the circuitry, which is critical for accurately tailoring cores.
Still others have reduced circuitry by checking for redundant connections. U.S. Pat. No. 4,816,999 "Method Of Detecting Constants And Removing Redundant Connections In A Logic Network" (issued Mar. 28, 1989 to Berman et al. and assigned to IBM Corp.) and U.S. Pat. No. 5,515,526 "Apparatus For Detecting Redundant Circuit Included In Logic Circuit And Method Therefor" (issued on Jun. 7, 1996 to Okuno and assigned to Mitsubishi) both disclose methods to eliminate redundant circuitry. With general purpose core designs, it is likely that redundant circuitry has already been removed, since cores are pre-designed and pre-verified. Thus, this group of patents does not specifically address the needs of tailoring ASIC cores.
To efficiently tailor core logic to serve the needs of each individual system on a chip, an automated means is required to reduce the labor requirements. To accurately tailor core logic, a method is needed which takes into account what application code will be the only code that used the core circuitry, that is, the application code to be embedded on the ASIC. Further, a method to accurately tailor core logic requires that core integrity be preserved for functions that might not be used in the normal application code execution, but which are needed for auxiliary purposes such as testing and error recovery. None of the prior methods address these needs.
Given the growing use of system level integration or system on a chip ASIC designs, there is a need to be able to tailor core circuitry for use with embedded application code. Tailoring core circuitry for an individual design reduces power requirements, speeds up execution, and maximizes the number of applications that can be embedded on one silicon die. Tailored core circuitry will provide especially useful to battery-operated, hand-held electronic devices, which have power supply, size and weight limitations. As the use of such electronic devices grows, the need for an accurate and efficient method of tailoring cores to specific system on a chip designs will become more important.